[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[oc] Coding Conventions are up

Hi Folks,

As I had said earlier, there is a need to have a set of RTL coding 
styles (VHDL / Verilog) followed by all of us here.
Hence I am putting up my compact set of "Naming Conventions" / "Coding 
Styles" or what ever it may be called as.
I have attached an HTML file containing these conventions.

Any positive criticism / suggestion is welcome at harish@opencores.org

Damjan, lets wait for some time and see that these conventions become 
stable (In case if I need to take a second look at it depending upon the 
type of response from others). Later we can have this up on the web.

Regards
Harish


_____________________________________________________________
Tired of limited space on Yahoo and Hotmail?
Free 100 Meg email account available at http://www.dacafe.com
Title: Untitled
Coding Styles
There is no single naming convention used in the design community. Naming conventions are used to maintain the standards across the design group so that the code written is easily understandable and the designer can adhere to a set of rules which enhances the code readability. So everyone can have their own set of meaningful rules framed up to their conventions. A typical set of rules is shown below.

1. Signal Naming Conventions
  • Signal names can contain mixed case letters and numbers as well. Use of underscores is not permitted.
  • The first character indeed has to be an alphabet.
  • First three characters should indicate or convey the name of the driving module.
    • Control unit - "ctl"
    • Arithmetic logic unit - "alu"
    • Multiply Accumulate unit - "mac"
    • Data Address Generator - "dag"
  • Signal name should indicate whether it is a global signal(G) or a local signal(L).
  • Signal name should tell whether it is a bus(B), wire(W) or clock(C).
  • Signal name should also indicate whether it is a active high(1) signal or a active low signal (0).
  • Later the signal name should tell what it is intended to be.
A few examples bound with the above conventions can be,
  • "aluGB1augend"  -  What we understand by this is that the driving module is the ALU, it is an active high global signal, it is a bus and it is one of the operands to the ALU.
  • "macGW0overflow" - This tells us that the driving module is the MAC, it is an active low global signal, it is a wire and it is intended to modify the overflow flag of status reg whenever a overflow occurs in the MAC.

2. Conventions for variables and constatnts
  • Variable names can contain mixed case letters, numbers as well as underscores.
  • All constant names should be in upper case letters only. But it can also have numbers and underscores.
  • Variable and Constant names should exactly mean what they are supposed to do / behave.
3. Other Conventions
  • Entity names should contain lower case letters only and they should not exceed 10 characters.
  • Architecture names should be entity names followed by 3 letter suffix "beh" for behavioural description, "rtl" for rtl description or "str" for structural description.
  • All register names should begin with the actual register name and terminate with a 3 letter suffix "REG".
  • As far as possible try to use Generics.
  • Use good amount of meaningful constants, so that it increases the code readability.
  • Before starting coding, having the Block diagram of what is being done is good since it expects a thorough understanding of the module by you which inturn eases and cuts off your coding time / efforts.

Any positive Criticism is Welcome @
mailto: harish@opencores.org