[openip] Re: Fwd: [[oc] Coding Conventions are up ]

["Jamil Khatib" <khatib@ieee.org>]

Hi, I am forwarding this email to opencores mailing list just to give
you my comments but I prefere to reply to openipcore mailing list
because I want to get comments from some people there

Thanks

These are my comments on the conventions and my recommendations

1. what about Port names
2. what is the meaning of driving module is it the source of the
signal, but what about multiple drivers of the same signal.
3. 0,1 should not be used to show active high or low signals because
they make confusion with the array indexes so I prefer 'n' and 'p'
4. I liked the signal names you proposed and I want to clarify it more
xxxxAAAAnnnnnnnn where xxxx is four characters describing the driving
module, component or process???.  AAAA is four characters describing
the attributes of the signal.  nnnnnn is the name of the signal in
lower case.
5. AAAA should be devided into groups where each character describe a
signle atribute, [Bus,Clock,Wire,conTrol],[Global,Local],[Positive,Nega
tive],[criticaL signal,],[if it can be Z stated],[Resolved ,Unresolved
signal],[signal type should be one of the attributes,
std_logivc,integer,bit,.....] may be we can adopt the windows naming
convintions. it uses some kind of naming I mentioned here.
6. beh or behavior, str or structure. I agree that the architecture is
related to the entity name so we can use the second convintion but we
have to remmber that several architectures can be used to describe the
same entity and all may be structural or so. Another issue is the
synthesizable archs [syn], simulatable models[mod] and post
synthesis[pst] archs types of library used after synthesis "vital
[vtllb], technology specific library [techlb]" all should be considered.
7. Generics as constants all should be UPPER CASE


What about the Document style and its sections
I suggest the following sections and to use the latex format

1. comments
2. Generics and constants
3. Entity archs, configuration naming and packages
4. signal naming
5. variable naming
6. processes & blocks naming
7. procesdures and functions



> Hi Folks,
> 
> As I had said earlier, there is a need to have a set of RTL coding 
> styles (VHDL / Verilog) followed by all of us here.
> Hence I am putting up my compact set of "Naming Conventions" /
"Coding 
> Styles" or what ever it may be called as.
> I have attached an HTML file containing these conventions.
> 
> Any positive criticism / suggestion is welcome at harish@opencores.org
> 
> Damjan, lets wait for some time and see that these conventions become 
> stable (In case if I need to take a second look at it depending upon
the 
> type of response from others). Later we can have this up on the web.
> 
> Regards
> Harish
> 
> 
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