Re: [oc] Beyond Transmeta...

["Marko Mlinar" <Marko.Mlinar@campus.fri.uni-lj.si>]

> Power consumption would be in that the 1 bit processors are only used when
> bits change. It would probably have many of the advantages (if not more)
then
> Crueso because it would only execute the relational instructions when a
bit
> changes, but does not execute any more, while most processors do a lot of
> redundant work.
Since you are SW guy I should warn you: in CMOS there is practicaly no
redundant
power consumption, since gates consume power only when changed. No extra
circuits are neccessary...

> Like I was saying above, the processor only needs to do minimal
operations,
> instead of calculating every bit over and over again, it can calculate
only
> the bits that have changed, and of course the network could possibly be
> configured for less power consumption and altered performance. So if it
only
> needs 10 1bit processors for one period of time and 32 1bit processors
> another, then the ability to use less power may be possible.
There is no need for 10 bit processors. Your network have to build '32b
instructions',
since compiler doesn't really know whether you will use only 10b in 'int'...

> One way to imagine it, is if you made an application in hardware, not
using
> instructions but using logic gates. That seems tuff, but if you had a
> compiler that would convert your code into a network (and vice versa),
then
> you would benefit from it.
>
> One of the big reasons I am here, is that I want to figure out or get a
good
> idea how hardware would deal with this, from that I could probably build a
> simulator that would allow me to start experimenting with creating
networks
> that act like processors, and start experimenting with creating an
assembler
> within the system. If I start compiling one now
I don't think that there is any problem of making it in HW (except routing),
but there are still problems in arhitecture itself.