[oc] WISHBONE DMA/Bridge UPDATE

[Rudolf Usselmann <rudi@asics.ws>]

I have made many, many changes to the WISHBONE DMA/Bridge IP
Core. I have checked in the new code and specification. The
main highlights are:

 * Up to 31 DMA Channels
 * 2, 4 or 8 priority levels
 * Linked List Descriptors support
 * Circular Buffer support
 * FIFO buffer support
 * Software & Hardware handshake support
 * Automatic Cannel registers Reload support
 * Fully configurable

For more information, please visit:
http://www.opencores.org/cores/wb_dma/

The new datasheet is available here:
http://www.opencores.org/cores/wb_dma/dma_doc.pdf

Cheers !
-- 
rudi