[oc] Suggestion for all Verilog designers

[Gavin Hurlbut <gjhurlbu@beirdo.ott.uplink.on.ca>]

Hello, all.

I am primarily a VHDL user (since I learned it first, I stuck with it)...  I
have had a fair amount of success linking Verilog cores to my VHDL designs (in
Xilinx Foundation 3.1i) using the EDIF output of the synthesized Verilog, but
I have just run into a snag.

It seems that some Verilog designers like to call their signals "we_" to
indicate that they are active low.  There is a small problem with this,
however.  That is an invalid signal name in VHDL, and I can't possibly link
the cores.  I would like to request that all Verilog designers refrain from
using trailing underscores in their external signal names (i.e. the port
definitions of your core).  Please use "we_N" or something like that such that
your port name has a valid name in both Verilog and VHDL if someone black-boxes
your core.

In particular the one that I just ran into that with is the "mem_ctrl" core.


Thanks in advance :)

Gavin

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