Re: [oc] Output loading in digital circuit

[Steve Wilson <stevew@intrinsix.com>]

Let me try my hand at this - having designed boards in a past life.

One thing you might be seeing is the "test circuit" that was used to actually measure (or spice if
you like) the timing numbers represented in the device data sheet.   They have to quote something,
so usually represent what that something is relative too.
This allows you to scale your numbers if necessary OR use it as an absolute load number you don't
want to exceed in your own design.  Example: The test circuit had 50pf in it.  My design has 20 pf
of load estimated on the board between the I/O's and board trace.  I'm under their 50 pf number,
so I should see the worst-case delay or better guaranteed.

Does this help any?

Steve

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