[oc] sdram controller and clock issues

[Vimal Reddy <vimalreddy@yahoo.com>]

I was trying to use the SDRAM controller at open cores
with the Micron SDRAM MT48LC2M32B2 . The verilog model
for the SDRAm has the follwoing setup and hold
violatoins defined. So if I use the same clock for the
controller and the SDRAM I get setuphold violations
because when I issue a command from the controller it
violates the setup and hold times on the SDRAM model.
So what should be the clock that goes to the
controller
 and the SDRAM . I mean, what is the general
 practice.how should their phases be natched and how
would one recommend it be implemented.
          $setuphold(posedge Clk,    Cke,   tCKS,
  tCKH);
          $setuphold(posedge Clk,    Cs_n,  tCMS,
  tCMH);
          $setuphold(posedge Clk,    Cas_n, tCMS,
  tCMH);
          $setuphold(posedge Clk,    Ras_n, tCMS,
  tCMH);
          $setuphold(posedge Clk,    We_n,  tCMS,
  tCMH);
          $setuphold(posedge Clk,    Addr,  tAS, 
  tAH);
          $setuphold(posedge Clk,    Ba,    tAS, 
  tAH);
          $setuphold(posedge Clk,    Dqm,   tCMS,
  tCMH);
          $setuphold(posedge Dq_chk, Dq,    tDS, 
  tDH);
  
  thanks,
  vimal
 


=====
Vimal Reddy
Graduate Student 
Computer Engineering
North Carolina State University
Raleigh, NC
Ph: (919) 859 5920

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