[oc] WISHBONE Rev.B3 released.

[Richard Herveille <richard@asics.ws>]

The WISHBONE System-on-Chip Interconnect Architecture Rev.B3 specifications 
have been released today. The specifications have been extended with a number 
of new transfer types called WISHBONE Registered Feedback Cycles, while the 
transfer types defined in the Rev.B2 spec have been renamed to WISHONE 
Classic Cycles.
The WISHBONE Registered Feedback Cycles greatly improve performance for 
IP-cores with registered ACK, RTY, and ERR signals, while maintaining fully 
compatible with WISHBONE Classic cycles.
Go to the wishbone pages http://www.opencores.org/wishbone/ to download the 
specs.

Richard

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