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Re: [oc] VHDL Simulation Model for 24C02

To: cores@opencores.org
Subject: Re: [oc] VHDL Simulation Model for 24C02
From: Richard Herveille <richard@asics.ws>
Date: Wed, 25 Sep 2002 12:44:25 +0200
In-Reply-To: <PMEMIGIPECNBEHOIPGOCAEFGCEAA.robert.taubner@sigmatek.at>
References: <PMEMIGIPECNBEHOIPGOCAEFGCEAA.robert.taubner@sigmatek.at>
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Try to translate the verilog model.

> Hi,
>
>  has anyone a VHDL simulation model for a I2C serial EEPROM eg. Microchip
> 24C02C ?
> If so please send a link.
>
> Regards,
>
> Robert

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References:
- [oc] VHDL Simulation Model for 24C02
  - From: "Robert Taubner" <robert.taubner@sigmatek.at>

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