Re: [oc] Design Question

[John Sheahan <jrsheahan@optushome.com.au>]

On Mon, Feb 03, 2003 at 08:40:21AM +0100, Richard Herveille wrote:
> > * The IP core I found is in Verilog but I am going to use vhdl language
> > for my design files. Does it matter whether IP core is in verilog and rest
> > of my application files are in VHDL?. Is there any design constrains,
> > pros. and cons. regarding this issue?
> 
> Not really, most synthesis tools can handle mixed-language designs. There 
> might be a few minor issues. For example Verilog allows a signal name to end 
> with a '_', VHDL pukes on this. However these issues should be simple to 
> resolve.

Depends also on what the synthesis tool license is. The free (beer) ones are
a lot more flexible than the commercial licenses here. wierd.
john
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