Re: [oc] Verilog

["Jim Dempsey" <tapedisk@ameritech.net>]

> also keep in mind that a || ~a && b is like a || b

If && and || evaluated left to right then

    a || ~a && b is like ~0&&b, or simply b (~0 is all ones)

    ((a || (~a)) && b)
    ((all 1's) && b)   (all 1's same as ~0)
    b

If && and || evaluated right to left (RPN) then result is not simply
anything.

Each bit must be evaluated.

    (a || ((~a) && b))

----- Original Message -----
From: "Illan Glasner" <IGlasner@mrv.com>
To: <cores@opencores.org>
Sent: Monday, February 10, 2003 3:51 PM
Subject: RE: [oc] Verilog


> Hi,
>
>    ~ come before & and & come before | , with the exception of ( ) ,
> therefore
>
> A <= ((B & C) | (D & E & ((~F) | (F & G)) & (~H)));
>
> also keep in mind that a || ~a && b is like a || b
>
> have a nice day
>
>    Illan
>
> -----Original Message-----
> From: Ho, Wen Jei x4297 [mailto:who1@rockwellcollins.com]
> Sent: Monday, February 10, 2003 9:22 AM
> To: OpenCores (cores@opencores.org)
> Subject: [oc] Verilog
>
>
>
> Somebody in OpenCore wrote something like:
>
> A <= B & C | D & E & (~F | F & G) & ~H;
>
> Could Verilog guru put in "(" and ")" for me?
>
>
>
> Thanks, Wen
>
>

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