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Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1
Aloha!
teju-dj@attbi.com wrote:
> Hence, it is more a design style, rather than should or should not. In
> many cases, if a designer already have a handful of well define blocks
> (Flops, Muxes, FIFOs,.... ) in his library, why shouldn't he just use #
> (parameter) to instantiate blocks? It really cuts down a lot in the
> development time and it also helps to avoid bugs.
Yes it's clearly a design style and above all a methodology issue. Most places
I've seen doing major ASIC design and want to instanciate cores with different
parameters instead use Perl or similar language to generate the correct RTL
code based on a template. Basically removing the parameter replacement from
all parsers. Everything is naturally versioned so that you can backtrack and
repeat.
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Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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