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Re: [oc] Verilog coding style for Open Cores-RTL - Case in point SHA1
At 08:43 21/05/2003 +0200, you wrote:
>Aloha!
>
>Marco Antonio Simon Dal Poz wrote:
>>I am used to do FPGA hardware design with Verilog and VHDL, and I can't
>>see why Verilog is so better than VHDL. In fact, I see advantages and
>>disadvantages in both sides, so, why Verilog is still dominant?
>
>On purely technical merits, and based on what you want to do (simulation
>model RTL-model for synthesis, GTL representation etc) each language have
>ther pros and cons. And it is more or less a moot point to try and analyze
>why Verilog dominates on purely technical merits. Instead it's IMHO things
>like:
I agree with you about the technical merits. I work usually with VHDL and i
cant compare VHDL-VERILOG deeply. VHDL is very powerfull not only as a
description language synthesis focused but sequential programming
(testbench, simulation, System Design) as well. I suppose that Verilog also
is powerful in those areas, but for investigation purposes VHDL is used
widely (see for example POLIS team [TABB00] B. Tabbara, A. Tabbara, A.
Sangiovanni-Vicentelli, Function / Architecture Optimization and Co-Design
of Embedded Systems, Massachusetts, USA: Kluwer Academic Publishers, 2000. ).
>* Historical. Verilog took off early as a design language. Companies like
>Intel, Cisco, Nortel etc all have built up huge data bases with cores and
>designs based on Verilog. Also these companies have huge setups/design
>flows and experience based on Verilog. All these means that you don't
>switch unless there are very compelling reasons. I.e. lots of money to be
>made. Instead these companies keep investing in Verilog.
>
>* Geographical. Most EDA tool vendors are based in the USA. Most ASIC/FPGA
>and EDA engineers in the USA use Verilog. For this reason, the Verilog
>version of tools are usually released first and have fewer bugs than the
>VHDL version.
Historical-Geographical reasons are very important here. Verilog USA / VHDL
Europe.
>* Market share. VHDL is generally found in academia, in Europe (but note
>that Verilog is very strong in Europe too) and for FPGA designs. For EDA
>vendors this means that the potential revenue for developing a VHDL
>version is quite slim. This is the main reason why Aart De Geus claimed
>that VHDL is dead.
>
>This all means that VHDL does not have industry support, neither from the
>major users and the major vendors. That's why Verilog is dominant and will
>continue to be.
I dont agree that Verilog is dominant everywhere. 100% of the companies and
Universities in my area uses VHDL. There are no Verilog seminars and all
the tools that the EDA vendors offer are for VHDL design.
>--
>Med vänlig hälsning, Yours
>
>Joachim Strömbergson - Alltid i harmonisk svängning.
>VP, Research & Development
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>
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