Re: [oc] Verilog coding style for Open Cores-RTL - Case in pointSHA1

[Charles Lepple <charles@motioncontrol.org>]

Rudolf Usselmann wrote:
> On Wed, 2003-05-21 at 03:39, Todd Fleming wrote:        
> 
>>Hello! I've been lurking on this list for several weeks now and thought I'd 
>>poke my head up here. I graduated from Virginia Tech. Like most schools, VT 
>>taught VHDL at the time but not Verilog. Now that I experiment with FPGAs I 
>>use Verilog; for some reason I just like it better. I don't know about other 
>>schools, but I do know why VT taught VHDL. A couple of the professors were on 
>>the VHDL specification committee. They are also the ones who taught the 
>>courses and wrote the book we used. There's a definite advantage to this; the 
> 
> 
> Something I never understood. Isn't it a conflict of interest
> if the Professor tells his students to buy a book that he wrote ?
> I mean it could be total crap, and nobody would know ....

It's a courtesy to the professor to use the book. A somewhat idealistic 
view is that local use of the textbook will help shake out any errors in 
the examples. In reality, it forces the student to either question the 
correctness of the information presented, or to just be lazy and hope 
for a curve because nobody bothered to figure out what the professor 
intended to say.

That's why some consider it "academic incest" to earn more than one or 
two degrees from the same school-- using your example, you would 
hopefully find out whether or not the book was "total crap" while 
studying at another institution.

-- 
Charles Lepple <charles@motioncontrol.org>

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