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[cvs-checkins] uart16550/bench/verilog uart_test.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] uart16550/bench/verilog uart_test.v
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Wed, 7 Nov 2001 19:02:31 +0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	01/11/07 19:02:31

Modified files:
	bench/verilog  : uart_test.v 

Log message:
	small update to test interrupts

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