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[cvs-checkins] pci/ tl/verilog/pci_pciw_pcir_fifos.v tl/veril ...

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	03/01/30 21:01:38

Modified files:
	rtl/verilog    : pci_pciw_pcir_fifos.v pci_wb_master.v 
	                 pci_wbw_wbr_fifos.v 
	bench/verilog  : system.v 
	sim/rtl_sim/run: run_pci_sim_regr.scr 

Log message:
	Updated synchronization in top level fifo modules.

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