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To: ecc@opencores.org
From: zhu.xiangyang@mail.zte.com.cn
Date: Tue, 5 Dec 2000 08:36:55 +0800
Reply-To: ecc@opencores.org
Sender: owner-ecc@opencores.org



'A 64KHZ clock is generated by gapping a 72KHZ clock'.
How to gapping a clock?  Can it be done by verilog/VHDL?

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