Re: [openrisc] Address pipeline during exception...

["Damjan Lampret" <lampret@opencores.org>]

> Well, that's one I hadn't thought about. So, to
> restate the obvious, you're telling me that whenever
> I execute an instruction through the DIR I actually
> change the PC and the instruction that was scheduled
> is ignored?
>
> That's a pretty important detail to leave out of the
> manual. That should definitely be added immediately.

Can you add this? (I'm right now working on some other cores as well)

> This is great for you, but it doesn't solve my problem.
> I want a cycle to cycle accurate simulator of Or1200
> so that I can port operating systems. I'm not looking

Why cycle accurate simulator? This will only create problems? Architecture
of the processor family is interface between software and between hardware.
If you want to run software and depend on low level characteristics of
specific hardware implementation, your software will not run on other
implementations. This is why every processor manufacturer developing new
processor family defines architecture first.
You should read implementation manual only when you want to exploit
particular hardware features that are not defined by architecture.

> l.ld     r7,(r6)
> l.sys   200
>
> Now, assume that (r6) is not in the cache, and a
> cache miss occurs. At what point is the system call
> actually performed? Before or after r7 has been
> resolved?  There could be a 12-14 bus cycle delay
> before r7 is actually valid. This could be pushing
> 100 CPU cycles in a fast core.

System call exception happens after cache refill and after r7 is valid. How
many cycle it takes

>
> I can answer this myself  *IF* I understand how
> you've implemented the pipelines.  I really need this
> document. In the case above, I would assume that
> r7 must be invalid, and that an attempt to use it
> would stall.

Of course it is valid. It MUST be valid. This is what ARCHITECTURE
specifies. However it isn't possile to answer your question about exact
timings because they depend on external memory.

>
> This is an important question for the following reason:
> As a good programmer porting an operating system,
> I need to understand if I can use the r7 register in
> the system call without incurring a pipeline stall. That
> will affect how I write my exception handler. It will
> affect how I tell gcc to allocate registers. It will have
> serious consequences in many aspects of design.

You will tell gcc how to allocate registers?

Why don't you write a generic port that will work on all OpenRISC 1000
implementations and won't rely on OR1200 internal document. How will RTEMS
work on superscalar OR? Will you have to rewrite it? If you would follow
architecture, it will work on all openrisc implementations that follow
architecture. If something is missing from the architecture, please point
that out and please ADD that to the manual (Word file is in the CVS).

>
> Every processor manual I've worked with includes
> a section on the pipeline, latencies, and execution
> units used by every single instruction.

That is "user manual" usually used by HW people. If you look at architecture
manual of I386 you won't find anything about latencies and other internal
information that is different for each implementation. I386 architecture
manual are 3 fat books with some 300 pages in each book. If you look at PPC
architecture manual, you'll again see stack of paper w/o any information
about instruction execution times etc.

regards,
Damjan