Re: [openrisc] Re: PC as GPR?

["Marko Mlinar" <markom@opencores.org>]

> You are using a PLD here, aren't you? Part of this discussion also
> touched on adding floating point and other instructions. I would
> think that a generic instruction extension capability would be in
> order. Something like that in the NIOS processor. Or if that
> doesn't fit in with the design then consider the Escape sequence
> used on the 8086 and like processors. For the string instructions
> and block operations you would incorporate the instructions in
> logic using possibly a DMA core in conjunction with a limited
> FIFO (to byte align the operations). QED
I am not sure at what exaclty are you aiming at, but or1k architecture
document defines floating point instructions and there is still a lot of
space for special instructions. Escape sequences would just destroy
the whole concept of simple RISC with instruction length always = 32b.

best regards,
Marko


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