Re: [openrisc] Question on breakpoint method

[Marko Mlinar <markom@opencores.org>]

> 1. If you take OpenRISC reference platform (ORP) SoC sources as an example,
> you will see that OR1200 with enabled *instruction* cache will not see trap
> instructions set by development interface. Possible ways how to fix this
> would be to either signal the IC to disable itself automatically when trap
> is set, invalidate cache line that development interface is seeting, or
> implement hardware memory cache coherency. The easiest way would be to
> implement memory cache coherency using a dual port RAM, but that has a
> consequence some technology issues when targetting ASIC using certain ASIC
> memory vendors. At the moment for debugging to work properly (ie to set
> breakpoints), IC needs to be disabled. FYI data cache doesn't have any
> relation to breakpoints.
Yes, if you still wish to use cache you can invalidate specific IC register 
via gdb.
If you wish you can add the code to gdb.

Marko

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