RE: [openrisc] Bugs detected on or1ksim

["Robert Cragie" <rcc@jennic.com>]

It seems to me that the outcome is still unclear on this.

As far as I can tell, the correct strategy is to clear the interrupt at the
*source* of the interrupt. You should NOT have to write a '1' to the
corresponding bit in the PICSR as well UNLESS the interrupt specifically
represents a latched transient condition. Even in this case, writing a '1'
to the corresponding bit in the PICSR is simply a convenient way of
effectively clearing the interrupt at source.

Robert Cragie, Design Engineer
_______________________________________________________________
Jennic Ltd, Furnival Street, Sheffield, S1 4QT,  UK
http://www.jennic.com  Tel: +44 (0) 114 281 2655
_______________________________________________________________

> -----Original Message-----
> From: owner-openrisc@opencores.org
> [mailto:owner-openrisc@opencores.org]On Behalf Of Scott Furman
> Sent: 09 June 2003 20:02
> To: openrisc@opencores.org
> Subject: Re: [openrisc] Bugs detected on or1ksim
>
>
> Damjan Lampret wrote:
>
> >And the manual was changed at that time. This is what correctly
> the manual
> >(in opencores cvs) says about PICSR:
> >
> >PICSR is used to determine the status of each interrupt input.
> Bits in PICSR
> >represent the status of the interrupt inputs and the actual
> interrupt must
> >be cleared in the
> >device, which is the source of the interrupt.
> >
> >
> I agree that the manual is correct.  I think the part that is missing is
> that the interrupt must be cleared in both the device that generated the
> interrupt *and* in the PIC.
>
> -Scott
>
>
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