Re: [oc] I'd be happy to participate and answer WISHBONE relatedquestions.

["Wade D. Peterson" <wadep@silicore.net>]

Hello Rudi:

To the best of my knowledge nobody has done any good research on SoC bus market
share.  My feeling is that these buses are just too new to get any good data.
For example, both CoreConnect and WISHBONE were released on the same day in June
of '99 at the DAC show in New Orleans.  That's only about a year and a half ago,
and it takes some time to develop infrastructure and design wins.

In fact, we're pretty clueless about WISHBONE market share ourselves.  We
provide all of the materials free from our website, so there's no good way to
track usage or individual users.  However, I can tell you for sure that: (a)
both we and our clients are using the bus, (b) we routinely field questions from
people who are using or evaluating the technology (including companies like
Erickson and Siemens) and (c) on the average we deliver 3-5 copies of the
WISHBONE spec from our website everyday (30-40 when there are newsgroup
discussions and so forth).

We haven't done any direct comparisons between these buses ourselves. However,
we have compiled a list of all the SoC buses that we're aware of at:
http://www.silicore.net/uCbusum.htm.

Here are some things that I suggest you include on your comparisons:

1) Licensing arrangements.  Even though some companies don't charge for their
technology, they do make you sign a license agreement.  For example, we looked
at one of the companies on your list, and they had a license agreement that
stated that they could revoke our license at anytime, for (apparently) any
reason.  That was too much for us to accept, so we dropped the deal.  If we had
ever decided to compete with that company's own cores, then they probably would
have dropped us like a hot potato.  Too risky!

2) Choice of interconnection architecture.  If you follow the traditional
microcomputer bus industry, you'll find that the hottest technologies right now
are the crossbar switches.  We believe the same thing is happening in SoC.  We
arranged the 'zippers' in WISHBONE so an IP core can be used in a traditional
Von Neumann (like AMBA or CoreConnect), data flow (FIFO), or crossbar switch
architecture.  This gives the system integrator a lot more flexibility.

3) Ease of use.  I know this is somewhat subjective for your comparison, but
we've seen some good results from people who have used WISHBONE for the first
time.  For example, an engineer at one of our very good clients just did a
remarkable WISHBONE SoC on an FPGA.  He is an analog designer with limited FPGA
experience.  However, he just completed a design with 2 WISHBONE masters and 8
slaves.  He wrote all of his system components using AHDL (we had never done
that before), and fully tested everything as a system.  To me this was
vindication that both WISHBONE and SoC can be simple.  I'm also tickled that he
did his design using low cost tools on a desktop PC.  Pretty cool.

Hope this helps!

Best regards,

Wade D. Peterson
Silicore Corporation
6310 Butterworth Lane
Corcoran, MN  USA  55340
TEL: (763) 478-3567, FAX: (763) 478-3568
URL: www.silicore.net  E-MAIL: wadep@silicore.net


----- Original Message -----
From: Rudolf Usselmann <rudi@asics.ws>
To: <cores@opencores.org>
Cc: Wade D. Peterson <wadep@silicore.net>
Sent: Monday, January 01, 2001 8:02 AM
Subject: Re: [oc] I'd be happy to participate and answer WISHBONE
relatedquestions.


>
> Hi Wade !
>
> I'm writing up a comparison document at the moment for SoC busses. We have
> chosen AMBA, CoreConnect and Wishbone as our favorites. Now I am trying to
> do a final analysis of all three busses and will post it soon to the
> discussion group.
>
> Information that seems really hard to come by is marketing type of stuff.
> Do you have any data as to market share of these busses ? Which & how many
> companies (besides the craetors ARM, IBM, Silicore) are using them ?
>
> Also, any direct comparison you might have I'd be willing to take a look
> at, even though I have already created my own comprehensive list (and
> opinions :*).
>
> Cheers !
> rudi
>
>
> on 1/1/01 18:46, Wade D. Peterson at wadep@silicore.net wrote:
>
> > Hello all...
> >
> > I just became aware that there is a discussion going on about WISHBONE on
this
> > reflector.  I understand that this group is evaluating WISHBONE as a SoC
> > interconnect, and thought I'd jump in with my two-cents worth.  Since I did
> > most
> > of the work on the spec, I thought I'd make myself available for questions
and
> > so forth.  However, I must apologize in advance if I'm not on target right
> > away,
> > as I haven't been following this thread until now.
> >
> > By the way - there is a Revision B WISHBONE spec in the works (it's about
half
> > done).  Right now, these are the things that will be changing:
> >
> > (1) Incorporate technical feedback from users, including: (a) additional
RULEs
> > about WISHBONE DATASHEET (supported cycles, bus widths and clock speed
> > requirements); (b) clear up questions about acknowledge timing.  (2) Add a
> > comprehensive index in the back.  (3) Change name from 'WISHBONE
> > Interconnection
> > Architecture For Portable IP Cores' to 'WISHBONE System-On-Chip (SoC)
> > Interconnection Architecture for Portable IP Cores'.  (4) Add 'WISHBONE
> > COMPATIBLE' logo.  (5) Standardize printing and covers. (6) Correct
> > typographical errors, change standard font to Times New Roman 12 pt, change
> > 'WISHBONE' to all capital letters.  (7) Change steward address.  (8) Add
> > appendcies with application notes.  (9) Move the glossary to chapter 1.
> >
> > My plan is to have this done over the next week or two.  However,  if there
> > are
> > comments or suggestions for this group, then I'd be happy to incorporate
them
> > in
> > the next spec.
> >
> > Best regards,
> >
> > Wade D. Peterson
> > Silicore Corporation
> > 6310 Butterworth Lane
> > Corcoran, MN  USA  55340
> > TEL: (763) 478-3567, FAX: (763) 478-3568
> > URL: www.silicore.net  E-MAIL: wadep@silicore.net
> >
> >
> >
> >