Re: [oc] PLL vs DLL

[Richard Herveille <richard@asics.ws>]

> Estimado mayank,
>
> Con fecha miércoles, 26 de febrero de 2003, 8:06:29, escribió:
>
> mdb> or the full control on clock delays & clock phases,which
> mdb> architecture is preferrable PLL or DLL.i know tht each one has its
> mdb> advantages,but both altera & Xilinx claims tht their PLL(in
> mdb> stratix) & DLL(in virtex or spartan-IIE) architecture has an edge
> mdb> over other.getting large multiples of frequencies in PLL is also
> mdb> an added advantage.where i can find the comparison between the
> mdb> two.
>
>    I have no answer for your question, but i can tell you DLL are faster
> and better than PLL, the only thing is that PLL have much more resolution
> than DLL.

So you have absolutely no underlying arguments, but you can tell us that DLLs 
are better ??? Are you a Xilinx fan??

As said before both have their advantages and disvantages. DLLs can be 
generated using pure digital blocks, you need some analog stuff for PLLs 
(e.g. VCO). Due to the analog nature, PLLs usually require separate power/gnd 
pins that need some special attention. DLLs have some build in hysteresis, 
because the delay is digital - fixed delay steps -, but cannot generate 
arbitrary frequencies, nor can they lock on any arbitrary input signal.
The DLLs fixed delay can cause the clock to jump, meaning the output clock 
doesn't have a nice 50/50 duty cycle. For a PLL this translates into jitter, 
I think I read something like plus/minus 500ps.

OK now what is better, a PLL or a DLL? I guess the answer is, depends on the 
application and/or your preference.

If you want to compare Altera's PLL and Xilinx DLL, check their websites. They 
both tell you why their choice is the better one. So you know the strengths 
and the weaknesses of both.

Richard


>
>    Cheers
>
>
> mdb> --
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