[oc] Video Timing generator(RS170) interlaced in VHDL help

[edwinstuff@yahoo.com]

I'm currently working on the Video Timing generator(RS170) in VHDL and 
have problem on the interlaced mode.

I know how the non-interlaced mode work but I couldn't get the 
interlaced mode to work.  
 
As I know, even scanning will have half of clock cycle earlier than odd
scanning on the front porch. Is that it?  what else I have to consider?  
The Video board still doesn't recognized it's a interlaced mode all the 
time.

Tried to find information about it but couldn't find it.  Any help is greatly 
appreciated. thanks

edwinstuff@yahoo.com
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