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Quartus-II (Was: Re: [oc] Verilog coding style...)
Aloha!
Rudolf Usselmann wrote:
>>Oh, and Altera Quartus-II did choke on the port value redefinition.
>>"Unsupported Verilog HDL Feature Error".
>
> I'll add this to mi list of "Why do I not use Alteras Quartus
> Software. The first item is it filled up a 10GB hard disk trying
> to "compile" a 100K gate design ! While my full custom ASIC tools
> have a hard time filling up a 4GB partition for a 2.5M gate ASIC.
> Hmm, makes you sometimes wonder wat's in their "Design Guideline" !
FWIW I ran the code on the Quartus-II 2.2SP2 version and then it went through,
so the latest and greatest version seems to suppport this (standard) feature.
Also, in terms of synthesis results, speed and scaleablility I would say that
Quartus-II have made quite some strides. Synplify has the edge, but the
difference is getting slimmer.
I'd even venture that it's much more productive to tweak the RTL to match the
target technology (in Alteras case for example, a good use of the large mem
blocks and partitioning in stacks of four MUXes) than switching synhtesis tools.
We are running quite a few 200+ kGate designs in Quartus-II and does not see
10 GB files and excessive memory usage. OTOH most tools have pathological
border cases. Case in point, I was able to nuke Cadence Build Gates Extreme
with a 5 kGate block earlier this spring. A tool I'm otherwise extremely fond
of BTW.
--
Med vänlig hälsning, Yours
Joachim Strömbergson - Alltid i harmonisk svängning.
VP, Research & Development
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